1. Field of Invention
The present invention relates to an EEPROM structure. More particularly, the present invention relates to a method for manufacturing EPROM tunnel oxide (ETOX) cell that will not result in any damages to its source region.
2. Description of Related Art
Electrically erasable programmable ROM (EEPROM) is a kind of memory that is now extensively used in computers and electronic products. The advantage of EEPROM is its ability to retain written programs and data permanently, yet can reuse those memory spaces by erasing those programs and data. The erase operation is simple. One only has to pass an electric current into the memory circuit for a predefined period. Fresh new data or programs can then be re-programmed in and stored. Moreover, memory store, erase and read operations can be repeated many times and can be carried out in a bit-by-bit manner, and so an EEPROM is very similar to a disk drive functionally. Additionally, another kind of EEPROM memory known as flash memory developed by Intel that operates in a block-by-block manner is now in the market. Although data have to be modified one block at a time, its fast operational speed is more than compensated by this minor defect.
FIGS. 1A through 1C and FIGS. 2A through 2C are various top and cross-sectional views showing the progression of manufacturing steps in producing a conventional ETOX cell. FIG. 1A is a top view showing the initial layout in ETOX cell fabrication. FIG. 1B is a cross-sectional view along line AA' of FIG. 1A, and FIG. 1C is a cross-sectional view along line BB' of FIG. 1A.
First, as shown in FIGS. 1A, 1B and 1C, a substrate 10 is provided. Then, a local oxidation of silicon (LOCOS) method is used to form field oxide layers 12 above the substrate 10 to define the device area. Next, a gate oxide layer 14 (tunnel oxide layer) is formed above the substrate 10 using a thermal oxidation method. Thereafter, a polysilicon layer preferably having a thickness of about 1000 .ANG. is formed covering the whole substrate structure using, for example, a low-pressure chemical vapor deposition method. Then, a dielectric layer 18 is formed over the polysilicon layer, wherein the dielectric layer 18 can be an oxide/nitride/oxide (ONO) composite layer. Subsequently, the dielectric layer 18 and the polysilicon layer are patterned to remove the dielectric layer and polysilicon layer lying above the device area, and forming a polysilicon layer 16. Finally, a substrate structure as shown in FIGS. 1A through 1C is obtained.
FIGS. 2A through 2C are top and cross-sectional views showing the subsequent stage in the manufacturing of a conventional ETOX cell. FIG. 2A is a cross-sectional view along line AA' of FIG. 2C, FIG. 2B is a cross-sectional view along line BB' of FIG. 2C and FIG. 2C is a top view of the final layout.
Next, as shown in FIG. 2A and FIG. 2B, high concentration of ions are implanted into the source region inside the device area to form a buried ion-implanted region 19. Subsequently, thermal oxidation is carried out to grow a gate oxide layer above the source region. Oxide layer formed by the thermal oxidation is thicker in areas above the source region because the source region has heavily doped ions. Thereafter, a layer of polysilicon preferably having a thickness of about 3000 .ANG. is deposited over the whole substrate structure to form a second polysilicon layer 21 using, for example, a low-pressure chemical vapor deposition method. After that, an oxide layer 22 is deposited over the second polysilicon layer 21 using, for example, an atmospheric pressure chemical vapor deposition method. The oxide material for forming the oxide layer 22 can be TEOS oxide, for example.
Thereafter, using the dielectric layer 18 as an etching stop layer, conventional photolithographic and etching processes are used to pattern the second polysilicon layer 21 and the oxide layer 22. Thus, the second polysilicon layer 21 becomes a control gate. In the subsequent step, a self-aligned source terminal etching operation is carried out to pattern the first polysilicon layer 16 into a floating gate. Then, a common source region is formed above the substrate 10. Finally, a complete substrate structure is formed whose top view is shown in FIG. 2C.
In the above method, since the dielectric layer 18 does not form a good protective layer for the first polysilicon layer 16, subsequently formed substrate structure will have data storage problems. Hence, few manufacturers will use this method to fabricate flash memory.
Furthermore, in using a conventional manufacturing method, a trench will be formed above the common source region of the substrate 10. This trench will cut off normal connection between common source regions, and will lead to functional abnormality of ETOX cell. Furthermore, even connection between common source regions still exists; damages caused by etching will raise the resistance in the common source regions. Hence, read/write efficiency of an ETOX cell will be lowered.
To reduce damages caused by the trench, one method is to increase junction depth of the source region. However, this will reduce the effective channel width of an ETOX cell, leading to difficulties in reducing ETOX cell dimensions.
In light of the foregoing, there is a need to provide a method for manufacturing ETOX cell that will not damage the source region.